Machine Learning algorithms demand efficient, high-speed hardware for real-time inference and training. Systolic Arrays (SAs) have become the architecture of choice in ML accelerators — including Google's TPU — owing to their inherent data parallelism and regular structure.
Conventional systolic arrays suffer from high critical-path delay, excessive area complexity, and high dynamic power consumption — bottlenecks that this project directly addresses through dual-radix factorization.
Six concrete design goals drive the ADR-SA architecture.
A comprehensive review of ten significant works in systolic array design and ML accelerator optimization was conducted across IEEE TVLSI, IEEE TCAS-II, ACM/IEEE DAC, and other leading venues.
| # | Author(s) | Year | Venue | Key Contribution |
|---|---|---|---|---|
| 01 | K. Inayat, I. Ullah, J. Chung | 2024 | IEEE TVLSI | Radix-8 factored SA for ML — significantly improves area, power, and delay over conventional SAs in resource-constrained environments. |
| 02 | H. Lee, J. Park, S. Kang | 2024 | IEEE TVLSI | Area-efficient redundancy for systolic arrays — high fault coverage and low area overhead for dependable edge AI accelerators. |
| 03 | M. A. Shafique, K. Inayat, J. A. Lee | 2023 | HEART Symp. | CSA-based radix-4 Gemmini SA — higher speed, lower latency, and better energy efficiency with minimal area overhead. |
| 04 | K. Inayat, J. Chung | 2022 | IEEE TVLSI | Hybrid accumulator FSA — improved throughput and energy efficiency over standard systolic designs. |
| 05 | H. Waris, C. Wang, W. Liu, F. Lombardi | 2021 | IEEE TCAS-II | Approximate radix-8 Booth multipliers for FPGA — significant delay and energy improvements with minimal accuracy loss. |
| 06 | K. Inayat, J. Chung | 2021 | Electronics | CPA-factored Gemmini SA — reduces latency and energy usage in ML acceleration hardware. |
| 07 | I. Ullah, K. Inayat, J.-S. Yang, J. Chung | 2020 | ACM/IEEE DAC | Radix-8 factored SA for tensor processing — higher throughput and lower arithmetic redundancy in tensor operations. |
| 08 | Z.-G. Liu, P. N. Whatmough, M. Mattina | 2020 | IEEE CAL | Systolic tensor array with structured sparsity — enhances inference speed and reduces power for mobile AI systems. |
| 09 | S. Ryu, N. Park, J.-J. Kim | 2019 | IEEE TVLSI | Feedforward-cutset-free pipelined MAC — higher speed, lower latency, better energy efficiency for ML accelerators. |
| 10 | A. A. Del Barrio, R. Hermida | 2017 | DATE Conf. | Slack-based deployment of radix-8 Booth multipliers — minimizes area and critical path delay while maintaining performance. |
The ADR-SA extracts Booth encoding and hard-multiple generation from individual Processing Elements and shares them at the input stage. The Radix-4 Adder replaces the conventional CPA in the accumulation stage.
| Y(i+1) | Y(i) | Y(i−1) | Mi | Operation |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0X |
| 0 | 0 | 1 | +1 | +1X |
| 0 | 1 | 0 | +1 | +1X |
| 0 | 1 | 1 | +2 | +2X |
| 1 | 0 | 0 | −2 | −2X |
| 1 | 0 | 1 | −1 | −1X |
| 1 | 1 | 0 | −1 | −1X |
| 1 | 1 | 1 | 0 | 0X |
| A | B | C | D | Operation |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0X |
| 0 | 0 | 0 | 1 | +1X |
| 0 | 0 | 1 | 1 | +2X |
| 0 | 1 | 0 | 1 | +3X |
| 0 | 1 | 1 | 1 | +4X |
| 1 | 0 | 0 | 0 | −4X |
| 1 | 0 | 1 | 0 | −3X |
| 1 | 1 | 1 | 0 | −1X |
The RD4A processes two bits simultaneously, reducing propagation delay and power versus a traditional binary adder. It has 5 inputs (Cin, Ai, Ai+1, Bi, Bi+1) and 3 outputs (Cout, Sumi, Sumi+1).
All synthesis results obtained under identical Xilinx ISE conditions — Speed Grade: −7, 8-bit operands, same device target.
| Metric | CPA (Carry Propagate) | CSA (Carry Select) | Radix-4 Adder | Best |
|---|---|---|---|---|
| Area (Gates) | 1916 | 1988 (+3.76%) | 1703 (−11.11%) | Radix-4 |
| Power (mW) | 243 | 223 (−8.23%) | 207 (−14.81%) | Radix-4 |
| Delay (ns) | 8.800 | 8.696 (−1.18%) | 4.755 (−45.97%) | Radix-4 |
| Max Freq (MHz) | 113.636 | ~115 | 210.305✦ Best | Radix-4 |
| 4-Input LUTs | 275 | — | 222 | Radix-4 |
The 3×3 ADR-SA was implemented and verified in ModelSim. Data moves sequentially from one PE to the next with synchronized computation. Power rises linearly (not exponentially), confirming linear scalability.
The ADR-SA integrates two complementary optimizations — Radix-8 Booth encoding and a Radix-4 Adder — to simultaneously address the three core bottlenecks of conventional systolic arrays. The result is a balanced, scalable architecture validated under identical Xilinx ISE synthesis conditions.
The 3×3 ADR-SA array-level simulation confirms functional correctness and linear scalability, making the ADR-SA a strong candidate for energy-constrained ML accelerators in edge computing, image processing, NLP, and video compression applications.
Presented at the National Conference on Sustainable Engineering Research & Applications (NCSERA-2026), Feb 26–27, 2026, organized by Avinashilingam Institute for Home Science and Higher Education for Women, Coimbatore.
Certificate of Presentation
Paper titled "Adaptive Dual-Radix Precision Systolic Architecture for Energy-Aware Machine Learning Acceleration" presented by Priyanka Gandhi A, Dept. of ECE, School of Engineering, Avinashilingam Institute, under the track Sustainable Biomedical Devices and Communication Technologies.
Project Timeline
Watch data tokens propagate through the 3×3 PE grid in real-time, synchronized to the clock edge.
Verilog HDL — Processing Element (PE)
Animated bars show the relative performance of CPA, CSA, and Radix-4 Adder across all three metrics.
Delay (ns) — lower is better
Power (mW) — lower is better
Area (gates) — lower is better